1.4 Modeling in VHDL
There are two main types of modeling in VHDL which are:
1.4.1 Behavioral Modeling
Sequential statements are executed in sequence. Changing the order of the
statements will change the outcome, but concurrent statements are executed based
on the flow of signal values. Changing the order of the statements will not change
the outcome.
A comparison between sequential and concurrent modeling is shown in the
following example:
Concurrent Entity XNOR2 is Port (A, B:in std_logic; Z: out std_logic); End XNOR2; Architecture concurrent of XNOR2 is -- signal declaration (of internal -- signals X, Y) Signal X, Y: std_logic; Begin X <=A and B; Y <= ( not A) and (not B); Z <= X or Y; End concurrent; | Sequential Entity XNOR2 is Port (A, B: in std_logic; Z: out std_logic); End XNOR2; Architecture sequential of XNOR2 is Begin XNOR2 : Process (A,B) Begin If ((A = '0' and B= '0') I (A = '1' and B= '1')) then Z<= '1’ ; Else Z <='0'; End if; End process xNOR2; End sequential; |
1.4.1.1 Sequential Modeling
The Process is the basis for sequential modeling, a process uses sequential
statements to describe the behavior of a system over time, and the syntax for a
process statement is as follows:
[Process label]: Process [(Signal sensitivity list)] [is]
[Process declarations]
Begin
List of sequential statements such as:
Signal assignments - variable assignments - Case statements - exit statements - if
statements - Loop statements - next statements - null statements - Wait statements
- procedure calls
End process [process label]
A process is declared within architecture and is a concurrentstatement; however
the statements inside a process are executed sequentially. The sensitivity list is a set
of signals to which the process is sensitive. Any change in the value of the signals in
the sensitivity list will cause immediate execution of the process.
Variables and constants that are used inside a process must be defined in the
process declarations part before the keyword begin, variable assignments inside a
process are executed immediately and denoted by the ":=" operator, while Signal
assignments are denoted by "<=" and changes occur after a delay.
If Statements
The If statement executes a sequence of statements depending on one or more
conditions, the syntax is as follows:
If condition then
Sequential statements
[Elsif condition then
Sequential statements]
[Else
Sequential statements]
End if;
The if statement is performed by checking each condition in the order they are
presented until a "true" is found, this statement must be inside a process construct.
Is often used to implement Finite State Machines ( FSM ) .
Example
Entity MUX_4_1a is
Port (S1, S0, A, B, C, D: instd_logic;
Z: out std_logic);
End MUX_4_1a;
Architecture ALGORITHMIC_IF of MUX_4_1a is
Begin
P1 : Process (S1, S0, A, B, C, D)
Begin
If S1='0' and S0='0' then
Z <= A;
Elsif S1='0' and S0='1' then
Z <= B;
Elsif S1='1' and S0='0' then
Z <= C;
Elsif S1= ' 1 ' and S0= ' 1 ' then
Z <= D;
End if;
End process P1;
End ALGORITHMIC_IF;
Case Statement
The case statement executes one of several sequences of statements, based on the
value of a single expression, the syntax is as follows:
Case expression is
When choices =>
Sequential statements
When choices =>
Sequential statements
[When others =>
Sequential statements )
End case;
The case statement evaluates the expression and compares the value to each of the
choices, the when clause corresponding to the matching choice will have its
statements executed, there is no two choices can overlap (i.e. each choice can be
covered only once). If the "when others" choice is not present, all possible values of
the expression must be covered by the set of choices.
loop Statements
The loop statements are used to repeatedly execute a sequence of sequential
statements, iteration schemes defined by the VHDL:
Basic-loop
While-Loop
For-Loop
[loop label:] Iteration scheme loop
Wait Statement
Sequential statements
[Next [label] [when condition];
[Exit [label] [when condition];
End loop [loop_label];
This loop has no iteration scheme. It will be executed continuously until it
encounters an exit or next statement, the basic loop (as well as the while-loop) must
have at least one wait statement. The nextstatement terminates the rest of the
current loop iteration and execution will proceed to the next loop iteration, while
the exit statement skips the rest of the statements, terminating the loop entirely,
and continues with the next statement after the exited loop.
Example
entity COUNT31 is
Port (CLK : in std_logic;
COUNT : out integer);
End COUNT31;
Architecture AlGORITHMIC_B_lOOP of COUNT31 is
Begin
P_COUNT: process
Variable intern_value: integer :=0;
Begin
COUNT<= intern_value;
loop
Wait until CLK='1';
intern_value := (intern_value + 1) mod 32;
COUNT<= intern_value;
End loop;
End process P_COUNT;
End ALGORITHMIC_B_lOOP;
A wait statement has been included so that loop will execute every time the clock
changes from '0' to '1', then we defined a variable intern_value inside the process
because output ports cannot be read inside the process.
While-Loop Statement
The while-loop evaluates a Boolean iteration condition. When condition is TRUE ,the
loop repeats, otherwise the loop is skipped and the execution will halt, the syntax is
as follows:
[Loop label:] While condition loop
Wait Statement
Sequential statements
[Next [label] [when condition];
[Exit [label] [when condition];
End loop [loop label];
The condition of the loop is tested before each iteration, including the first iteration.
If it is false, the loop is terminated,
For-loop Statement
The for-loop uses an integer iteration scheme that determines the number of
iterations, the syntax is as follows:
[loop label:] for identifier in range loop
sequential statements
[Next [label] [when condition];
[Exit [label] [when condition];
End loop [loop_label];
The value of the identifier can only be read inside the loop and is not available
outside its loop, the range must be a computable integer range in one of the
following forms:
VHDL Tutorial - LESSON 2