1.4.1.2 Concurrent Statements
The dataflow modeling describes a circuit in terms of its function and the flow of data
through the circuit, concurrent signal assignments arc event triggered and executed as
soon as an event on one of the signals Occurs, several concurrent constructs are used in
dataflow modeling which are :
Simple Concurrent Signal Assignments
The syntax is as follows:
Target signal <= expression
The value of the expression is transferred to the target signal, and the type of the
target signal has to be the same as the type of the value of the expression.
Examples:
Sum <= (A xor B) xor Cin;
Carry <= (A and B);
Z <= (not X) or Y after 2 ns;
Conditional Signal Assignments
The syntax is as follows
Target signal <= expression when Boolean condition else
expression when Boolean condition else
expression;
The target signal will receive the value of the first expression whose Boolean
condition is TRUE, If no condition is found to be TRUE, the target signal will receive
the value of the final expression, and if more than one condition is true, the value of
the first condition that is TRUE will be assigned.
An example of a 4-to-1 multiplexer using conditional signal assignment is shown below .
Entity MUX_4_1_Conc is
Port (S1, S0, A, B, C, D: instd_logic;
Z: out std_logic);
End MUX_ 4_1_Conc;
Architecture DATAFlOW_CSA of MUX_ 4_1_Conc is
Begin
Z <= A when S1='0' and S0='0’ else
B when S1='0' and S0='1' else
C when S1='1' and S0='0' else
D;
End DATAFLOW_CSA;
Selected Signal Assignments
The syntax is as follows
with choice expression select
Target name <= expression when choices,
Target name <= expression when choices,
.
.
[Target name <= expression when others];
The expression selected is the first with a matching choice, there is no two choices can
overlap, and all possible values of choice expression must be covered by the set of
choices, unless an others choice is present.
An example of a 4-to-1 multiplexer using selected signal assignment is shown below.
Entity MUX_ 4_1 is
Port (A, B, C, D: in std_logic;
SEL: in std_logic_vector(1 down to 0);
Z: out std_logic);
End MUX_ 4_1;
Architecture DATAFlOW_SSA of MUX_4_1is
Begin
With SEL select
Z <= A when "00",
B when"01”,
C when"10",
D whenothers;
End DATAFLOW_SSA;
1.4.2 Structural Modeling
A structural way of modeling describes a circuit in terms of components and its
interconnection, it is a very good way to describe complex digital systems, though a set
of components in a hierarchical fashion, but at the lowest hierarchy each component
must be described as a behavioral model, hierarchical design approaches are always
preferred over flat designs. They result in reduced complexity; structural modeling
involves component declaration, instantiation and interconnections
Component Declaration
The component declaration consists of the component name and the interface
(ports).
The syntax is as follows:
Component component_name [is]
Port (port_signa I_names: modetype;
port_signal_names: mode type;
.
.
port_signal_names: mode type);
End component [component_name];
The component name refers to either the name of an entity defined in a library or
an entity explicitly defined in the VHDL file (see example). If the component is
declared in the package, no need to declare it in the architecture.
Component Instantiation
The component instantiation statement initiates an instance of the component
already defined, the syntax is as follows:
Instance name: component name
Port map (signal1, signaI2, ...,signaln);
The instance name is the name of this particular instance. While the component
name is the name of the component declared earlier using the component
declaration statement, and the signal name is the name of the signal to which the
specific port is connected.
The first port in the component declaration corresponds to the first signal (signal1),
the second port to the second signal (signaI2), etc. The signal position must be in the
VHDL Tutorial - LESSON 3