1.5 Data objects
1.5.1 Constants
Constants (and Variables) are used to model the behavior of a circuit and are used in
processes. A constant can have a single value of a given type and cannot be changed
during the simulation. Constants can be declared at the start of an architecture or
within a process. constants are declared as follows:
constant name_of_constant: type := value;
1.5.2 Variables
A variable can have a single value, as with a constant, but a variable can be updated
using a variable assignment statement. Variables must be declared inside a process.
The variable is updated without any delay as soon as the statement is executed.
The variable declaration is as follows:
variable variable_name: type [ := initial value]
1.5.3 Signals
Signals can be considered wires in a schematic that can have a current value and
future values. Signals are updated when their Signal assignment statement is
executed, after a certain delay.
Signals are declared with the following statement:
1. 6 data types
The type defines the set of values that the object can have and the set of operations
that are allowed on it.
Several data types are used in VHDL:
Data types defined in the standard package (bit - bit vector - integer - real - Boolean ...)
Enumerated types: Consists of lists of character literals (std_ulogic - std_logic ...)
The different values that a std_logic object can have are:
'U'-- Uninitialized 'X' -- Forcing unknown
'0' -- Forcing 0 '1' --Forcing 1
'Z' -- High impedance 'w' -- Weak unknown
'L' -- Weak 0 'H' -- Weak 1
'-' -- Don't care
User-defined Types
Composite Types (Array and Record)
1.7Attributes
Attributes are used to return various types of information about a signal, variable or
type. Attributes consist of a quote mark (') followed by the name of the attribute.
Slgnal_name 'event : returns the Boolean value True if an event on the signal
occurred, otherwise gives a False. signal_name ’last_value: gives the value of the
signal before the last event occurred on the signal.
An example of an attribute is
If CLOCK' event and CLOCK = '1' then
This expression checks for the arrival of a positive clock edge.
1.8 Operators
The different classes of operators in VHDL are:
Shift operators :
These operators perform a bit-wise shift or rotate operation on a one-dimensional
array of elements of the type bit (or std_logic). The operand is on the left of the
operator and the number (integer) of shifts is on the right side of the operator.
Examples:
variable A: bit_ vector := "101001" ;
A sll 2 results in "100100"
A srI 2 results in "001010"
A sla 2 results in “100111"
A sra 2 results in "111010"
A rol 2 results in "100110"
VHDL Tutorial - LESSON 4