2.2 Sequential Circuit Design Example :
The circuit under study will be a Counter. We will design three counters, a
synchronous one using JK Flip-Flops and counts from 0 up to 6 .
2.2.1 Counter using JK Flip-Flops
2.2.1.1 Excitation Tables and Karnaugh Maps
Karnaugh Maps:
"J0" Map
"K0" Map
"J1" Map
"K1" Map
"J2" Map
"K2" Map
2.2.1.3 Boolean Expression
2.2.1.3 VHDL Behavioral Code of Inverter
library ieee;
use ieee.std_logic_1164.all;
Entity invert is
Port (a : in std_logic;
b:out std_logic);
end invert
Architecture invbehave of invert is
Begin
b <= not (a);
end invbehave;
2.2.1.4VHDL Behavioral Code of 2-input AND
library ieee;
use ieee.std_logic_1164.all;
Entity and2i is
Port (a,b : in std_logic;
c:out std_logicl;
end and2i
Architecture andbehave of and2i is
Begin
c <= a and b;
end andbehave;
2.2.1.5 VHDL Behavioral Code of 2-input OR
library ieee;
use ieee.std_logic_1164.all;
Entity or2i is
Port (a,b : in std_logic;
c:out std_logic);
end or2i
Architecture orbehave of or2i is
Begin
c <= a or b;
end orbehave;
2.2.1.6 VHDL Behavioral Code of JK Flip-Flop
library ieee;
use ieee.std_logic_1164.all:
Entity jkff is
Port (j,k,clk : in std_logic;
q:out std_logic);
end jkff
Architecture behavelikethis of jkff is
signal q_int : std jogic := '0';
Begin
Process (clk)
Begin
If clk='1' and clk 'eventthen
If j='1' and k='0' then
q_int<='1';
elsif j='0' and k='1' then
q_int<='0';
elsif j='1' and k='1' then
q_int<=not (q_int);
end if;
end if;
end process;
q<=q_int;
end behavelikethis
2.2.1.7 VHDL Structural Code of the JK Flip-Flops Counter
library ieee;
use ieee.std_logic_1164.all;
Entity jkcount is
Port (clk: in std_logic;
q0,q1,q2:out std_logic);
end jkcount
Architecture Structural of jkcount is
signalq0int,q1int,q2int,q1i,q2i,j0,k0,j1,k1,j2,k2 : std_logic := '0';
Component invert is
Port (a : in std_logic;
b:out std_logic);
end Component
Component and2i is
Port (a,b : in std_logic;
c:out std_logic);
end Component
Component or2i is
Port (a,b : in std_logic;
c.out std_logic);
end Component
Component jkff is
Port (j,k,clk : in std_logic;
q:out std_logic);
end Component
begin
inv0: invert
port map (q1int,q1i)
inv1 : invert
port map(q2int,q2i)
and0 : and2i
port map(q0int,q1int,j2)
or0: or2i
port map(q1i,q2i,j0)
or1 : or2i
port map(q0int,q2int,k1)
jk0 : jkff
port map(j0,l,clk,q0int)
jk1 : jkff
port map(q0int,k1,clk,q1int)
jk2 : jkff
port map(j2,q1int,cIk,q2int)
q0 <= q0int;
q1 <= q1int;
q2 <= q2int;
end Structural
VHDL Tutorial - LESSON 6